Usually, you have to decide how many bits in the register you want to dedicate to the integer part of the number vs the fractional part of the number. Since all of the coefficient values are less than one, all 15 bits (the MSB of the total 16 bits is the signed bit) of my registers can be dedicated to fractional bits. The next thing to address is how to handle the coefficient values in Verilog, the decimal point values need to be converted to fixed point values. To set these values as signed data type in Verilog, the keyword signed is used: reg signed register_name These values are also all signed, thus the MSB is used as the sign bit and the lower remaining bits are what the value must fit into (be sure to keep this in mind when selecting the initial widths of the input sample register). Now after deciding on the order (number of taps) for your FIR and obtaining your coefficient values, the next set of parameters that must be defined is the bit width of the input samples, output samples, and the coefficients themselves.įor this FIR, I chose to set my input sample and coefficient registers to be 16 bits wide and my output sample register to be 32 bits since the product of two 16-bit values is a 32-bit value (the widths of the two values being multiplied add to give the width of the product, so if I had chosen 16-bit input samples with 8-bit taps then the output samples would be 24 bits wide). One of the simplest examples of this is the low pass filter, which allows frequencies below a certain threshold (cutoff frequency) to pass while greatly attenuating frequencies above that threshold, as depicted in the figure below. The role of any filter is for signal conditioning, mainly focusing on the selection of which frequencies to either filter out or allow to pass through. A FIR's transfer function contains no feedback, so if you feed in a single impulse of value 1 followed by a bunch of zero values, the output will simply be the coefficient values of the filter. This amount of time that it takes the impulse response to settle to zero is directly related to the order of the filter (the number of taps) which is the order of the FIR's underlying transfer function polynomial. Thus, in this mini-series on the practical way of getting started with DSP basics on FPGAs, I'm going to start with a simple 15-tap low pass filter FIR that I generate the initial coefficient values for in Matlab then convert those values for use in a Verilog module.Ī finite impulse response or FIR filter is defined as a filter with an impulse response that settles to a zero value over a certain period of time, thus making it finite. The humble FIR filter is one of the most basic building blocks in digital signal processing on an FPGA, so it's important to know how to throw together a basic module of one with a given number of taps and their corresponding coefficient values.
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